PCB for conversion of USB HDD to SATA interface (Free)

[fzabkar]

Many years ago I saw a photo of a USB-to-SATA conversion that was obviously done by someone who had never heard of differential pairs or characteristic impedance. The wires must have been about 30cm long and they were just thrown about like a rat's nest. Apparently they still managed to retrieve the data. IIRC, this was a tutorial on the SalvationData web site.

Found it:

https://www.datarecoverytools.co.uk/2010/05/05/how-to-connect-and-recover-usb-only-western-digital-drives-with-hd-doctor-suite/

[sin]

Lol. Some one should try something similar with a charger

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[fzabkar]

This stuff does my head in.

High-Speed I/O Design Guidelines:
https://www.asset-intertech.com/resources/blog/2012/03/high-speed-io-design-guidelines/

The ground wires in the SATA data cable are needed for crosstalk and interference reasons, not for data transmission, so one wonders why SalvationData bothered adding not 1, but 3, useless ground wires in their example.

[csava]

The impedance (including capacitive and inductive characteristics), wire length, EMI, and EMC effects have adverse factors that are positively correlated with the signal frequency. In the context of monolithic flash data recovery, I often encounter issues when connecting the monolith using wires. One common problem is irregular patterns or page shifts at the end of the bitmap. The typical solutions include adjusting the VCC voltage (power) or shortening the wire length to align the end of the page. However, these adjustments essentially address the longer rise time of the signal caused by the parasitic capacitance on the wires, which can lead to timing errors at certain moments. Adjusting the VCC voltage (power) and shortening the connection wires are physical adjustments at the physical layer. Additionally, other factors such as voltage thresholds and bus contention in the controller can contribute to this phenomenon.
https://support.rusolut.com/portal/en/k ... 17-11-2021

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[sin]

transmission lines, the most ignored topic.

However , honestly I know only RF part of transmission lines as a ham radio enthusiast. Don't want my expensive radios to fry

Excellent co-relation with flash. Many thanks.
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[Amarbir[CDR-Labs]]

transmission lines, the most ignored topic.

However , honestly I know only RF part of transmission lines as a ham radio enthusiast. Don't want my expensive radios to fry

Excellent co-relation with flash. Many thanks.
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Sir ,
I have only observe that voltage adjustment does make a difference ,Wire length will make a difference only if a guy is really a idiot .Monoliths behave like this only

[sin]

arrival time of signals and wire length is a pretty relent subject.

[sin]

relevant *

[csava]

This stuff does my head in.

High-Speed I/O Design Guidelines:
https://www.asset-intertech.com/resources/blog/2012/03/high-speed-io-design-guidelines/

The ground wires in the SATA data cable are needed for crosstalk and interference reasons, not for data transmission, so one wonders why SalvationData bothered adding not 1, but 3, useless ground wires in their example.

You are correct. In SATA transmission, the ground wire serves as interference protection rather than data transmission. This function is similar for all differential lines, such as PCIe signals. The ground wire represents a reference potential of 0 volts. If the ground wire is too long or if there are numerous corners in the return path, it can introduce electromagnetic compatibility issues. This is because the ground wire acts as an antenna, increasing the probability of electromagnetic radiation being received by the ground plane. According to the formula v= 12/√(ε_r) in/ns, the length of the conductor has a negligible impact on signal delay on the circuit board. However, the adverse effects caused by excessively long signal lines and ground wires are the most common problems in practical applications.

[pepe]

The impedance (including capacitive and inductive characteristics), wire length, EMI, and EMC effects have adverse factors that are positively correlated with the signal frequency. In the context of monolithic flash data recovery, I often encounter issues when connecting the monolith using wires. One common problem is irregular patterns or page shifts at the end of the bitmap. The typical solutions include adjusting the VCC voltage (power) or shortening the wire length to align the end of the page. However, these adjustments essentially address the longer rise time of the signal caused by the parasitic capacitance on the wires, which can lead to timing errors at certain moments. Adjusting the VCC voltage (power) and shortening the connection wires are physical adjustments at the physical layer. Additionally, other factors such as voltage thresholds and bus contention in the controller can contribute to this phenomenon.
https://support.rusolut.com/portal/en/k ... 17-11-2021

@csava's rusolut pic:

Such thing happened to me when i routed a monolith UFD or uSD to pc3k wire board, some people said cotroller needs to be cut, etc. The fact was that the controller had some impact on the clock signal level, driving it actively during inactive periods. Checking with oscilloscope i noticed the signal level is significantly reduced, so i thought the NAND fails to register each clock transition, resulting in such uncertainities.
Later i found that the bus drivers on the pc3k wire board have pretty low driving strength, like 4-6 mA as far as i recall. Started digging and found drivers being able to do 20-30 mA (rough numbers, i am lazy now to look it up in the ds).
after replacing the driver i got correctly aligned dump, clock signal looked a lot nicer too, of course.

pepe

[sin]

Exciting stuff PEPE!

How did you find the drive current was low? Where was the miliameter placed? In IO lines or VCC. Also what sort of a meter did you require if you placed the ammeter in IO lines? TRMS? and while measuring stuff what sort of signals did you send to the nand? I suppose it has to be a lengthy signal for taking an approximate agreeable reading..

Really cool stuff. It will be helpful to get the knowledge base expanded on this thread if you are willing to describe your approach.

Thanks
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[pepe]

no meter used. Oscilloscope revealed the signal level, it was fairly low because of the controller. After that i looked up the datasheet of the bus driver, got the drive current values from there.

[sin]

Ah nice

inseries DSO/CRO?

How did you manage to derive current(4-6mA) unless the impedance is known?

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[Amarbir[CDR-Labs]]

This stuff does my head in.

High-Speed I/O Design Guidelines:
https://www.asset-intertech.com/resources/blog/2012/03/high-speed-io-design-guidelines/

The ground wires in the SATA data cable are needed for crosstalk and interference reasons, not for data transmission, so one wonders why SalvationData bothered adding not 1, but 3, useless ground wires in their example.

You are correct. In SATA transmission, the ground wire serves as interference protection rather than data transmission. This function is similar for all differential lines, such as PCIe signals. The ground wire represents a reference potential of 0 volts. If the ground wire is too long or if there are numerous corners in the return path, it can introduce electromagnetic compatibility issues. This is because the ground wire acts as an antenna, increasing the probability of electromagnetic radiation being received by the ground plane. According to the formula v= 12/√(ε_r) in/ns, the length of the conductor has a negligible impact on signal delay on the circuit board. However, the adverse effects caused by excessively long signal lines and ground wires are the most common problems in practical applications.

Hi,
i urge everyone to checkout this video ,Ground Interference is discussed in details here though we are talking about logic analyzer ,We started this topic that the length of the sata wires can have interference and we are not following the design rules of PCB ,IMHO single sided PCB for this is enough ,Sin is yet to send me pcb for testing

The Link -> https://www.youtube.com/watch?v=xZ5wKYnCNcs

[csava]

The impedance (including capacitive and inductive characteristics), wire length, EMI, and EMC effects have adverse factors that are positively correlated with the signal frequency. In the context of monolithic flash data recovery, I often encounter issues when connecting the monolith using wires. One common problem is irregular patterns or page shifts at the end of the bitmap. The typical solutions include adjusting the VCC voltage (power) or shortening the wire length to align the end of the page. However, these adjustments essentially address the longer rise time of the signal caused by the parasitic capacitance on the wires, which can lead to timing errors at certain moments. Adjusting the VCC voltage (power) and shortening the connection wires are physical adjustments at the physical layer. Additionally, other factors such as voltage thresholds and bus contention in the controller can contribute to this phenomenon.
https://support.rusolut.com/portal/en/k ... 17-11-2021

@csava's rusolut pic:

Such thing happened to me when i routed a monolith UFD or uSD to pc3k wire board, some people said cotroller needs to be cut, etc. The fact was that the controller had some impact on the clock signal level, driving it actively during inactive periods. Checking with oscilloscope i noticed the signal level is significantly reduced, so i thought the NAND fails to register each clock transition, resulting in such uncertainities.
Later i found that the bus drivers on the pc3k wire board have pretty low driving strength, like 4-6 mA as far as i recall. Started digging and found drivers being able to do 20-30 mA (rough numbers, i am lazy now to look it up in the ds).
after replacing the driver i got correctly aligned dump, clock signal looked a lot nicer too, of course.

pepe

I have never tested driver current in the manner you described. If the testing method is correct, it should explain why there is a higher probability of page shifting when reading monolithic with the PC3000 flash Multiboard Adapter compared to FE. I tested three reading devices, and the PC3000 flash performed the worst in the tests, while VNR and FE showed similar performance. In most cases, VNR performed better than FE. I tried bridging the SN74LVC8T245PWR chip on the Multiboard Adapter with a wire, and it improved the reading effect. However, that would void the warranty. But for me, the warranty is meaningless as I should be able to repair it if the modification fails. So I disassembled the VNR as soon as I received it. The VNR uses 74ALVC541PW as a transceiver, and they are functionally similar. However, certain electrical performance parameters may contribute to the difference in reading performance. I compared the datasheets but couldn't find any clues. I thought it would be a good idea to create a modified Multiboard Adapter using the 74ALVC541PW and perform tests on it. But I got stuck when ordering the adapter interface. The supplier informed me that the interface (MOLEX DVI-60P) used by PC3000 flash has been discontinued for a long time and is no longer available. It's a sad story.

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[Amarbir[CDR-Labs]]

Csava ,
How about effect of multicom adapters in nand flash when its a monolith ,ever tried that too

[csava]

Csava ,
How about effect of multicom adapters in nand flash when its a monolith ,ever tried that too

The experiment I mentioned in the previous text is based on the results of a monolithic test. If a monolithic-specific adapter is used, the probability of encountering page offset will decrease. This is because the monolithic-specific adapter uses a PCB and probe instead of soldered wires, eliminating the interference variables mentioned above. You only need to consider whether the IO voltage threshold matches. However, the majority of monolithics do not have dedicated adapters, so soldered wires remain the primary workflow. I have designed and developed a suite specifically for monolithic data recovery, which is currently in the final stages of development. Once it is fully ready, I will release a new thread.

Attachments

[sin]

PCBs arrived. I must say what a commendable job to find out the exact placement of the connections. Posting results soon

sending one set + Jtagulator pcb to Amarbir tomorrow morning.


thanks a ton for uploading all the designs.

It will be honor to learn how did you accurately plot things..my guess is you used a 1:1 picture in your EDA and you took it from there with some experimentation.

fab work !
<3
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[Amarbir[CDR-Labs]]

Hey Guys ,
Looking Forward in assembling them and using them ,Lets see the results and how well it works and what mods we can do to it ,BTW Csava why do you need all the bells and whistles for reading small monolith cards ,What are those cards and what do they do

[csava]

Hey Guys ,
Looking Forward in assembling them and using them ,Lets see the results and how well it works and what mods we can do to it ,BTW Csava why do you need all the bells and whistles for reading small monolith cards ,What are those cards and what do they do

As we know, the biggest difference between Monolith data recovery and regular flash drive recovery is that Monolith devices require additional work to discover and connect the wire leads, which often consumes a significant amount of engineer's time. FlashMatrix can greatly simplify this process, allowing you to approach Monolith cases with the same ease and efficiency as regular flash drive recovery.
Additionally, the FlashMatrix database includes recovery workflow solutions for current Monolith device data recovery.
You simply need to filter out the Monolith images from the database that match your case, follow the provided configuration to connect the wires, and click on apply configuration. Afterwards, you can read the chip on your flash reader. Micro-soldering is the only skill you need to master in the entire process.